1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as a CMOS static RAM, and more particularly to a semiconductor integrated circuit capable of reducing power consumption.
2. Description of the Background Art
FIG. 9 is a circuit diagram for explaining a semiconductor integrated circuit according to the prior art. Japanese Patent Application Laid-Open No. 5-325566 has described, in detail, the contents shown in FIG. 9. In FIG. 9, BL1 and BL2 denote bit lines, MC0 denotes a memory cell connected to the bit lines BL1 and BL2, PCC0 denotes a precharge circuit connected to the bit lines BL1 and BL2 for precharging the bit lines BL1 and BL2 in response to a mode signal PCB, and SA0 denotes an electric potential converting circuit (a sense amplifier) connected to the bit lines BL1 and BL2 for amplifying, converting and outputting electric potentials of the bit lines BL1 and BL2.
The precharge circuit PCC0 includes PMOS transistors T1 and T2. V1 denotes a precharge potential.
The memory cell MC0 includes NMOS transistors T10 and T11. Electric potentials of nodes N1 and N2 represent data, one of which is at an "H" level and the other is at an "L" level.
The electric potential converting circuit SA0 includes PMOS transistors T4 and T5, and NMOS transistors T6 to T9, T31 and T32. GND denotes a ground potential, and V2 denotes a potential which is higher than the ground potential GND.
Mode signals PC and PCB are complementary to each other.
FIG. 10 is a timing chart showing operation of the circuit in FIG. 9. At a time t10, the mode signal PC, the mode signal PCB, an electric potential of a word line WL, the electric potential of the node N1 and the electric potential of the node N2 are at "H", "L", "L", "L" and "H" levels, respectively. At a time t11, the mode signal PC falls and the mode signal PCB rises. At a time t12, the electric potential of the word line WL rises. At a time t13, the mode signal PC rises, the mode signal PCB falls, and the electric potential of the word line WL falls. A period for which the mode signal PC is falling, for example, between the times t11 and t13, will be hereinafter referred to as a read mode, and other periods will be hereinafter referred to as a precharge mode.
With a circuit structure shown in FIG. 9, the transistors T4, T6, T31 and T7 are ON, OFF, OFF and OFF immediately before the time t13 that the precharge mode is started, respectively. In a state of transition from the read mode to the precharge mode, the mode signal PC first rises so that the transistor T6 is turned from OFF to ON. At the same time, the transistor T1 is turned from OFF to ON so that the bit line BL1 is precharged. The electric potential of the bit line BL1 is raised. However, a capacity of the bit line BL1 (including a capacity of the memory cell MC0) is particularly large. Therefore, the electric potential of the bit line BL1 is raised slowly.
At a time t14, the electric potential of the bit line BL1 is set to a threshold voltage of the transistor T31 so that the transistor T31 is turned from OFF to ON. At a time t15, the electric potential of the bit line BL1 is set to a threshold voltage of the transistor T4 so that the transistor T4 is turned from ON to OFF. Accordingly, the transistors T4, T6 and T31 are simultaneously turned ON between the times t14 and t15. Therefore, a current flows from the high potential V2 to the ground potential GND through these transistors.
In the circuit shown in FIG. 9, thus, a period for which the current flows into the electric potential converting circuit becomes long depending on a change in the electric potential of the bit line. Consequently, power consumption is increased.
Furthermore, Japanese Patent Application Laid-Open No. 6-12879 has described technology related to the electric potential converting circuit. In this technology, two sense amplifiers are provided and the number of elements is greater than in the electric potential converting circuit shown in FIG. 9. For this reason, a leak current or the like is easily generated and power consumption is increased.
As described above, the prior art has had a problem that the power consumption is increased in the electric potential converting circuit.